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# 15th LSI Design Contests・in Okinawa Design Specification - 6-1

## 6-1. Level1 :[128-point FFT]

In this level, designner must assume input signal coming in serially with HEAD signal as shown in figure 39. Design FFT circuit which generate FFT outputs and OUTHEAD signal with some latency. The latency is arbitrary.

Table 5: Pin list

FFT |
|||

Signal name | in or out | bit width | explanation |

CLK | IN | １ | Clock |

HEAD | IN | １ | '1' means the beginning |

FFTIN_I | IN | 8 | Input Real components (Unsinged Int,0-255) |

FFTIN_Q | IN | 8 | Input Imaginary components (Unsinged Int,0-255) |

OUTHEAD | OUT | 1 | '1' means the beginning |

FFTOUT_I | OUT | 14 | Output Real components, Keep 8-bit precision |

FFTOUT_Q | OUT | 14 | Output Imaginary components, Keep 8-bit precision |

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