library IEEE; use IEEE.STD_LOGIC_1164.all, IEEE.NUMERIC_STD.all; entity PARITY is port ( A : in unsigned(49 downto 0); Y : out std_logic ); end PARITY; architecture RTL of PARITY is begin process(A) variable TMP : std_logic; begin TMP := '0'; for i in 0 to 49 loop TMP := TMP xor A(i); end loop; Y <= TMP; end process; end RTL;