design_analyzer> report_area
Information: Updating design information... (UID-85)
 
****************************************
Report : area
Design : PARITY
Version: 1999.05
Date   : Tue Sep 14 14:24:03 1999
****************************************

Library(s) Used:

    class (File: /usr/open/synopsys/1999.05/libraries/syn/class.db)

Number of ports:               51
Number of nets:                99
Number of cells:               49
Number of references:           1

Combinational area:        147.000000
Noncombinational area:       0.000000
Net Interconnect area:      undefined  (Wire load has zero net area)

Total cell area:           147.000000
Total area:                 undefined