-- TESTBENCH for SRP

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

use WORK.ALU_PKG.all;

entity TEST_SRP is
end entity TEST_SRP;

architecture TESTBENCH of TEST_SRP is
  -- instruction read only memory IROM
    component IROM
	port (Add   : in  std_logic_vector (5 downto 0);
	      Dout  : out std_logic_vector (31 downto 0) );
    end component IROM;
  -- data random access memory DRAM
    component DRAM
	port (Add   : in  std_logic_vector (5 downto 0);
	      Clock : in  std_logic;
	      WE    : in  std_logic;
	      Din   : in  std_logic_vector (31 downto 0);
	      Dout  : out std_logic_vector (31 downto 0) );
    end component DRAM;
  -- minimips
    component SRP
	port (Clock    : in  std_logic;
	      Reset    : in  std_logic;
	      Iadd     : out std_logic_vector (5 downto 0);
	      Inst     : in  std_logic_vector (31 downto 0);
	      Dadd     : out std_logic_vector (5 downto 0);
	      WE       : out std_logic;
	      Wtdata   : out std_logic_vector (31 downto 0);
	      Rddata   : in  std_logic_vector (31 downto 0) );
    end component SRP;
  -- system clock
    signal  Clock  : std_logic := '0';
    signal cycles  : integer := 0;
  -- system reset
    signal  Reset  : std_logic := '1';
  -- wires on the board
    signal  Iadd   : std_logic_vector (5 downto 0);
    signal  Inst   : std_logic_vector (31 downto 0);
    signal  Dadd   : std_logic_vector (5 downto 0);
    signal  WE     : std_logic;
    signal  Wtdata : std_logic_vector (31 downto 0);
    signal  Rddata : std_logic_vector (31 downto 0);
    
begin
  -- clock generator while Iadd is less than 24.
    CLOCK_GEN: process 
    begin
        if (cycles < 10000) then  -- max 10000 cycles
	     cycles <= cycles +1;
	     wait for 50 ns;
	     Clock <= not Clock;
        else wait;
	end if;
    end process CLOCK_GEN;
  -- IROM
    ROM: IROM port map (Iadd,Inst);
  -- DRAM
    RAM: DRAM port map (Dadd,Clock,WE,Wtdata,Rddata);
  -- SRP MPU
    MPU: SRP port map (Clock,Reset,Iadd,Inst,Dadd,WE,Wtdata,Rddata);
  -- reset sequence
    RESET_SEQ: process
    begin
        wait for 100 ns;
	Reset <= '0';
    end process RESET_SEQ;
end architecture TESTBENCH;

configuration CFG_SRP of TEST_SRP is
    for TESTBENCH
    end for;
end configuration CFG_SRP;